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j)
k)
l)
m)
n)
o)
p)
If the host has not placed the result of its CRC calculation on D[15:0] since first driving D[15:0] during (9),
the host shall place the result of its CRC calculation on D[15:0] (see 6.5.4.5 ).
The host shall negate – DMACK no sooner than t MLI after the device has asserted DSTROBE and negated
DMARQ and the host has asserted STOP and negated – HDMARDY, and no sooner than t DVS after the host
places the result of its CRC calculation on D[15:0].
The device shall latch the host’s CRC data from D[15:0] on the negating edge of – DMACK.
The device shall compare the CRC data received from the host with the results of its own CRC calculation. If
a miscompare error occurs during one or more Ultra DMA burst for any one command, at the end of the
command, the device shall report the first error that occurred (see 6.5.4.5 ).
The device shall release DSTROBE within t IORDYZ after the host negates – DMACK.
The host shall neither negate STOP nor assert – HDMARDY until at least t ACK after the host has negated –
DMACK.
The host shall not assert – IORD, -CS0, -CS1, A2, A1, or A0 until at least t ACK after negating DMACK.
Figure 14: Ultra DMA Data-In Burst Host Termination Timing
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after
DMARQ and DMACK are negated.
6.5.4.4.6 Initiating an Ultra DMA Data-Out Burst
An Ultra DMA Data-out burst is initiated by following the steps lettered below. The timing diagram
is shown in Figure 15: Ultra DMA Data-Out Burst Initiation Timing. The timing parameters are
specified in Table 26: Ultra DMA Data Burst Timing Requirements and are described in Table 27: Ultra DMA Data
Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
a) The host shall keep – DMACK in the negated state before an Ultra DMA burst is initiated.
b) The device shall assert DMARQ to initiate an Ultra DMA burst.
c)
Steps I, (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
d) The host shall assert HSTROBE.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
Page 35 of 102
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